Benutzeranleitung / Produktwartung MC68HC08KH12 des Produzenten Freescale Semiconductor
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M68HC08 Microcontrollers freescale.com MC68HC08KH12 Data Sheet Rev. 1.1 MC68HC08KH12/H July 15, 2005.
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MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 3 Advance Information — MC68HC(7)08KH12 List of Sections Section 1. General Desc ription .......... ............................. 23 Section 2. Memory Ma p ...............
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 4 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 5 Advance Information — MC68HC(7)08KH12 Table of Contents General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 6 Freescale Se miconduc tor 2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 7 Section 7. System Integration Module (SIM) 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2 Introduction . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 8 Freescale Se miconduc tor 7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . 84 7.8.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . 85 Section 8.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 9 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 10 Freescale Se miconduc tor 9.5.7 USB Embedded Device Control Register 2 (DCR2) . . . . . 146 9.5.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7) . . . . . . . . . . . . . . . . . . .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 11 11.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 12 Freescale Se miconduc tor 12.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 202 12.8.2 Data Direction Register F (DDRF). . . . . . . . . . . . . . . . . . . 203 12.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 13 14.4.1 IRQ1 /V PP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 14.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 14 Freescale Se miconduc tor Section 16. Break Module (BREAK) 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.2 Introduction . . . . . . . . .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 15 17.12 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . . . 255 17.13 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 16 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 17 Advance Information — MC68HC(7)08KH12 List of Figures Figure Title P age 1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1-2 64-Pin QFP Assignments ( Top View) .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 18 Freescale Se miconduc tor Figure Title P age 7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-16 Wait Recovery from Interrupt or Br eak . . . . . . . .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 19 Figure Title P age 9-20 USB Embedded De vice Endpoint 0 Data Register (UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10-1 Monitor Mode Circuit.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 20 Freescale Se miconduc tor Figure Title P age 12-20 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 203 12-21 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 21 Advance Information — MC68HC(7)08KH12 List of Tables T ab le Title Pa ge 2-1 Vector Addresses .......... ................ ................. ................ .......... 43 7-1 Signal Name Convention s .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 22 Freescale Se miconduc tor T ab le Title Pa ge 12-1 I/O Port Register Summ ary............ ............................... .......... 184 12-2 Port A Pin Functions ...... ................ .......
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 23 Advance Information — MC68HC(7)08KH12 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 24 Freescale Se miconduc tor 1.2 Introduction The MC68HC(7)08KH12 is a member of the low-cost, high-performance M68HC08 Family of 8-bi t microcontroller units (MCUs). The M68HC08 Family is based on the customer-spec ified integrated circuit (CSIC) design strategy.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 25 • Full Universal Serial Bus Specif ication 1.1 Com posite HUB with Embedded 1 Functions: –1 × 12 MHz Upstream Port –4 × 12 MHz / 1.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 26 Freescale Se miconduc tor Features of the CPU08 include the following: • Enhanced HC05 Programming Model • Extensive Loop Co ntrol Function.
MC68HC(7 )08KH12 — Rev . 1.1 Adv ance Inf ormation Freescale Semicon ductor 27 Figure 1-1. MCU Block Diagram DS Port 1 ➀ PORTS ARE SOFTWARE CONFIGURABLE WITH PULLUP DEVICE IF INPUT PORT ➁ SOFTWA.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 28 Freescale Se miconduc tor 1.5 Pin Assignments 1.5.1 Quad Flat Pack (QFP) Package Figure 1-2 Shows the 64-pin QFP assignments.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 29 1.5.2 Power Supply Pins (V DDA , V SSA , V DD1 , V SS1 , V DD2 , and V SS2 ) V DDA and V SSA are the analog power suppl y and ground pins used by the on-chip Phase- Locked Loop circuit.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 30 Freescale Se miconduc tor 1.5.3 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins ar e the connections for the on-chip oscillator circuit. (See Section 8. Clock G enerator Module (CGM) .) 1.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 31 1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) PTA7–PTA0 are general-purpose bi directional I/O port pins. (See Section 12. I/O Ports .) Each pin contains a software configurable pull- up device when the pin is configured as an input.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 32 Freescale Se miconduc tor 1.5.13 Port F I/O Pins (PTF7/KBF7–PTF0/KBF0) PTF7/KBF7–PTF0/KBF0 are gener al-purpose bidirectio nal I/O port pins. (See Section 12. I/O Ports .) Any or all of the port F pins can be programmed to serve as ex ternal interrupt pins.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 33 Advance Information — MC68HC(7)08KH12 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 34 Freescale Se miconduc tor $0000 ↓ $005F I/O REGISTERS (80 BYTES) $0060 ↓ $01DF RAM (384 BYTES) $01E0 ↓ $CDFF UNIMPLEMENTED (52, 256 BYTES.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 35 2.3 I/O Section Addresses $0000–$005F, shown in Figure 2-2 , contain most of the control, status, and data registers.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 36 Freescale Se miconduc tor A d d r . N a m e B i t 7 654321 B i t 0 $0000 Port A Data Register (PTA) R: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 37 $0010 TIM Status and Control Register (TSC) R: TOF TOIE TSTOP 00 PS2 PS1 PS0 W: 0 TRST $0011 Unimplemented R: W: $0012 .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 38 Freescale Se miconduc tor $0020 USB Embedded Device Endpoint 0 Data Register 0 (DE0D0) R: DE0R07 DE0R06 DE0R05 DE0R04 DE0R03 DE0R02 DE0R01 DE0R.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 39 $0030 USB HUB Endpoint 0 Data Register 0 (HE0D0) R: HE0R07 HE0R06 HE0R05 HE0R04 HE0R03 HE0R02 HE0R01 HE0R00 W: HE0T07 H.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 40 Freescale Se miconduc tor $0040 Port F Keyboard Status and Control Register (KBFSCR) R : 0000 KEYFF 0 IMASKF MODEF W: ACKF $0041 Port F Keyboar.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 41 $0050 Unimplemented R: W: $0051 USB HUB Downstream Port 1 Control Register (HDP1CR) R: PEN1 LOWSP1 RST1 RESUM1 SUSP1 0D.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 42 Freescale Se miconduc tor $FE00 Break Status Register (BSR) R: RRRRRR SBSW R W: $FE01 Reset Status Register (RSR) R: POR PIN COP ILOP ILAD USB .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 43 Table 2-1 is a list of vector locations. 2.4 Monitor ROM The 240 bytes at addresses $FE 10–$FEFF are reserved ROM addresses that contain the instruct ions for the monitor functions.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 44 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 45 Advance Information — MC68HC(7)08KH12 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 46 Freescale Se miconduc tor During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack po inter decrements during pushes and increments during pulls. NOTE: Be careful when using nested subr outines.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 47 Advance Information — MC68HC(7)08KH12 Section 4. Read-Only Memory (ROM) 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 48 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 49 Advance Information — MC68HC(7)08KH12 Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 50 Freescale Se miconduc tor NOTE: The CONFIG register is a special r egister containing one-time writable latches after each reset. Upon a reset, the CONFIG register defaults to the predetermined settin gs as shown in Figure 5-1 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 51 Advance Information — MC68HC(7)08KH12 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 52 Freescale Se miconduc tor 6.3 Features Features of the CPU include the following: • Full Upward, Object-Code Com patibility with M68HC05 Fami.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 53 Figure 6-1. CPU Registers 6.4.1 Accumulator (A) The accumulator is a general-purpose 8- bit register. The CPU uses the accumulator to hold operands and th e results of arithmetic/logic operations.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 54 Freescale Se miconduc tor 6.4.2 Index Register (H:X) The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index regi ster, and X is the lower byte.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 55 6.4.3 Stack Pointer (SP) The stack pointer is a 16-bi t register that contains the address of the next location on the stack. During a rese t, the stack pointer is preset to $00FF.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 56 Freescale Se miconduc tor 6.4.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 57 6.4.5 Condition Code Register (CCR) The 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 58 Freescale Se miconduc tor I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 59 C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 60 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 61 Advance Information — MC68HC(7)08KH12 Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 62 Freescale Se miconduc tor 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 63 Figure 7-1. SIM Block Diagram STOP/WAIT CLOCK CONTROL CLOCK GENERATORS POR CONTROL RESET PIN CONTROL SIM RESET STATUS R.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 64 Freescale Se miconduc tor Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $FE00 Break Status Register (BSR) Read: RRRRRR SBSW R Write: Reset: 0 $FE.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 65 Table 7-1 shows the internal signal names used in this section. 7.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signal s for the CPU and peripherals on the MCU.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 66 Freescale Se miconduc tor 7.3.2 Clock Start-Up from POR When the power-on reset module generat es a reset, t he clocks to the CPU and peripherals are inactive an d held in an inactive phase until after the 4096 CGMXCLK cycle POR tim eout has completed.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 67 An internal reset cl ears the SIM counter (see 7.5 SIM Counter ), but an external reset does not. Each of th e resets sets a co rresponding bit in the reset status register (RSR).
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 68 Freescale Se miconduc tor Figure 7-5. Inter nal Reset Timing The COP reset is asynchro nous to the bus clock. Figure 7-6. Sources of Internal Reset The active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the MCU.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 69 Figure 7-7. POR Recovery 7.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR).
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 70 Freescale Se miconduc tor 7.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset st atus register (RSR) and causes a reset.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 71 7.5 SIM Counter The SIM counter is used by the pow er-on reset module (POR) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (I BUS) clocks.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 72 Freescale Se miconduc tor 7.6 Exception Control Normal, sequential progra m execution can be chang ed in three different ways: • Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instru ction (SWI) • Reset • Break interrupts 7.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 73 Figure 7-8. Interrupt Processing NO NO NO YES NO NO YES NO YES YES FROM RESET BREAK I BIT SET? IRQ1 INTERRUPT? USB INTERRUPT? FETCH NEXT INSTRUCTION UNSTACK CPU REGISTERS.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 74 Freescale Se miconduc tor At the beginning of an interrupt, the CPU sa ves the CPU register contents on the sta ck and sets the interrupt ma sk (I bit) to prevent additional interrupts.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 75 set, the SIM proceeds with interrup t processing; other wise, the next instruction is fetched and executed. If more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 76 Freescale Se miconduc tor 7.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 77 7.6.2.1 Interrupt St atus Register 1 I F 6–I F 1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt r equests from the sources shown in Table 7-3 .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 78 Freescale Se miconduc tor 7.6.2.2 Interrupt St atus Register 2 I F 11–I F 7 — Interrupt Flags 11–7 These flags indicate the presence of interrupt r equests from the sources shown in Table 7-3 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 79 7.6.3 Reset All reset sources always have equal and highest pr iority and cannot be arbitrated. 7.6.4 Break Interrupts The break module can st op normal program flow at a software- programmable break point by assert ing its break interrupt output.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 80 Freescale Se miconduc tor below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 7.7.1 Wait Mode In wait mode, t he CPU clocks are inactive while the peripheral clocks continue to run.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 81 Figure 7-16. Wait Recovery from Interrupt or Break Figure 7-17. Wait Recover y from Internal Reset 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 82 Freescale Se miconduc tor A break interrupt during stop mode sets the SI M break stop/wait bit (SBSW) in the break st atus register (BSR). The SIM counter is held in reset from the execution of the STOP instruction until th e beginning of stop recovery.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 83 7.8 SIM Registers The SIM has three memo ry mapped registers. Table 7-4 shows the mapping of thes e registers. 7.8.1 Break Status Register (BSR) The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 84 Freescale Se miconduc tor 7.8.2 Reset Status Register (RSR) This register contains six flags that show the sour ce of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clear s all other bits in the register.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 85 POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of RSR PIN — External Reset Bit 1 = Last res.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 86 Freescale Se miconduc tor BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the br eak state, the BCFE bit must be set.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 87 Advance Information — MC68HC(7)08KH12 Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 88 Freescale Se miconduc tor 8.6.4 PLL Referenc e Divider Select Register (PRDS) . . . . . . . . 106 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 89 8.3 Features Features of the CGM include: • VCO Center-Of-Range Frequuency t uned to 48 MHz for Low-Jitter Clock Refe.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 90 Freescale Se miconduc tor Figure 8-1. CGM Block Diagram BCS PHASE DETECTOR LOOP FILTER FREQUENCY DIVIDER VOLTAGE CONTROLLED OSCILLATOR AUTOMATI.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 91 8.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. The OSC1 pin is t he input to the amp lifier and the OSC2 pin is the output.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 92 Freescale Se miconduc tor The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bo und to a range from roughly 40 MH z to 56 MHz, f VRS .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 93 8.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically conf igurable into one of two operating modes: • Acquisition mode — In acquisition m ode, the filter can make large frequency corrections to the VC O.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 94 Freescale Se miconduc tor noise hit and th e software must take a ppropriate action, depending on the application.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 95 2. Choose a practical PLL (cr ystal) reference frequency, f RCLK , and the reference clock divider, R. Frequency errors to the PLL are corrected at a rate of f RCLK /R. For stability and lock time reduction, this rate must be as fast as possible.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 96 Freescale Se miconduc tor A zero value for R or N is interpreted exactly the same as a value of one. A zero value for L disabl es the PLL and prevents its selection as the source for the base clock.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 97 • Tuning capacitor, C 2 (can also be a fixed capacitor) • Feedback resistor, R B • Series resistor, R S (optional.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 98 Freescale Se miconduc tor 8.5 I/O Signals The following paragraphs descr ibe the CGM I/O signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 99 8.5.6 Buffered Crystal Clock Output (CGMVOUT) CGMVOUT buffers the OSC1 clo ck for external use.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 100 Freescale Se miconduc tor 8.6 CGM Registers These registers control and m onitor operation of the CGM: • PLL control regi ster (PCTL) (See 8.6.1 PLL Cont rol Register (PCTL) .) • PLL bandwidth control register (PBWC) (See 8.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 101 T ab le 8-2. CGM I/O Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $003A PLL Control Register (PCTL) Re.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 102 Freescale Se miconduc tor 8.6.1 PLL Control Register (PCTL) The PLL control register contains t he interrupt enable a nd flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power of two range selector bits.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 103 PLLON — PLL On Bit This read/write bit activates t he PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1).
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 104 Freescale Se miconduc tor 8.6.2 PLL Bandwidth Control Register (PBWC) The PLL bandwidth control register: • Indicates when the PLL is locked.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 105 logic zero and has no m eaning. The write one func tion of this bit is reserved for test, so this bit must always be written a zero.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 106 Freescale Se miconduc tor MUL[11:0] — Multiplier select bits These read/write bits control the m odulo feedback divider that selects the VCO frequency mu ltiplier N. (See 8.4.3 PLL Circuits and 8.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 107 8.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request ev ery time the LOCK bit changes state.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 108 Freescale Se miconduc tor 8.8.2 CGM During Break Interrupts The system integration module (SIM) c ontrols whether status bits in other modules can be cleared during th e break state.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 109 Other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 110 Freescale Se miconduc tor The most critical parameter which af fects the reaction times of the PLL is the reference frequency, f RDV . This frequency is the input to the phase detector and controls how often the PLL makes corr ections.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 111 8.9.3 Choosing a Filter Capacitor As described in 8.9.2 Parametric Infl uences on R eaction Time , the external filter capacitor, C F , is critical to the stabi lity and reaction time of the PLL.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 112 Freescale Se miconduc tor an initial frequency error, (f DES – f OR IG )/f DES , of not more th an ± 100 percent. NOTE: The inverse proportionality between the lock time a nd the reference frequency.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 113 Advance Information — MC68HC(7)08KH12 Section 9. Universal Serial Bus Module (USB) 9.1 Contents 9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 114 Freescale Se miconduc tor 9.2 Features Features of the gene ral USB Module include the following: • Integrated 3.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 115 Features of the embedded device f unction include the following: • Device Control Endpoint 0 a nd Interrupt Endpoint.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 116 Freescale Se miconduc tor Figure 9-1. USB Block Diagram 9.4 I/O Register Description of the HUB function The USB hub function prov ides a set of contro l/status registers and sixteen data registers that provide storage for t he buffering of data between the USB hub function and the CPU.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 117 T ab le 9-1. HUB Contro l Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0051 USB HUB Downstream Port 1.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 118 Freescale Se miconduc tor $005A Unimplemented Read: Write: Reset: $005B USB HUB Control Register 0 (HCR0) Read: TSEQ STALL0 TXE RXE TPSIZ3 TPS.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 119 T ab le 9-2. HUB Data Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0030 USB HUB Endpoint 0 Data Regis.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 120 Freescale Se miconduc tor 9.4.1 USB HUB Root Port Control Register (HRPCR) RESUM0 — Force Resume to the Root Port This read/write bit forces a resume signal (“ K” state) on to the USB root port data lines to initiate a remote wakeup.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 121 EOF2 is generated by KH12 every mill isecond, if SOF is not detected when three or more EOF2 has occurred, softwa re can set the SUSPND-bit and put KH 12 into suspend mode.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 122 Freescale Se miconduc tor bit can be set to 1 by the host reques t only. It can be cleared either by hardware when a fault condition was detected or by software through the host request. Re set clears this bit.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 123 SUSP1-SUSP4 — Downstream Port Selective Suspend Bit This read/write bit forces the downstream port entering the selective suspend mode. This bit can be set by the host request SetPortFeature (PORT_SUSPEND) only.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 124 Freescale Se miconduc tor SOFF — Start Of Frame Detect Flag This read only bit is set when a valid SOF PID is detected on the D0+ and D0– lines at the root port. Software must clear this flag by writing a logic 1 to SOFFR bit in the SIETSR register .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 125 SOFIE — Start Of Fr ame Interrupt Enable This read/write bit enabl es the Start Of Fr ame to generate a USB interrupt when the SOFF bit becomes set. Re set clears this bit.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 126 Freescale Se miconduc tor RSTF — USB Reset Flag This read only bit is set when a valid reset signal state is detected on the D0+ and D0- lines. This reset detecti on will also generate an internal reset signal to reset the CPU and other peripherals including the USB module.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 127 9.4.5 USB HUB Address Register (HADDR) USBEN — USB Module Enable This read/write bit enabl es and disables t he USB module. When USBEN is cleared, t he USB module will not respond to any tokens and the external regul ated output REGOUT will be turned off.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 128 Freescale Se miconduc tor 9.4.6 USB HUB Interrupt Register 0 (HIR0) TXDF — HUB Endpoint 0 Data Transmit Flag This read only bit is set after the data stored in HUB Endpoint 0 transmit buffers has been sent an d an ACK handshake packet from the host is received.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 129 TXDIE — HUB Endpoint 0 Tr ansmit Interrupt Enable This read/write bit enables the Transmit H UB Endpoint 0 to generate CPU interrupt requests when the TXDF bit becomes set.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 130 Freescale Se miconduc tor TSEQ — HUB Endpoint 0 Transmit Sequence Bit This read/write bit deter mines which type of da ta packet (DATA0 or DATA1) will be sent during the next IN tr ansaction directed at Endpoint 0.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 131 TPSIZ3-TPSIZ0 — HUB Endpoint 0 Transmit Data Packet Size These read/write bits st ore the number of trans mit data bytes for the next IN token request fo r HUB Endpoint 0.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 132 Freescale Se miconduc tor PCHG5-PCHG0 — HUB and Po rt Status Change Bits These read/write bits report the st atus change for the Hub, embedded device and the four downstream ports. The Status Change Bitmap is returned to the host th rough the HUB endpoint 1 if the bit PNEW is 1.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 133 RSEQ — HUB Endpoint 0 Receive Sequence Bit This read only bit indica tes the type of data packet last received for HUB Endpoint 0 (DAT A0 or DATA1).
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 134 Freescale Se miconduc tor 9.4.10 USB HUB Endpoint 0 Data Registers 0-7 (HE0D0-HE0D7) HE0Rx7-HE0Rx0 — HUB Endpoint 0 Receive Data Buffer These read only bits are serially loaded with OUT token or SETUP token data directed at HUB Endpoint 0.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 135 T ab le 9-3. Embedded De vice Control Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0047 USB Embedded .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 136 Freescale Se miconduc tor T ab le 9-4. Embedded Device Data Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0020 USB Embedded De.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 137 $0028 USB Embedded Device Endpoint 1/2 Data Regi ster 0 (DE1D0) Read: Write: DE1T07 DE1T06 DE1T05 DE1T 04 DE1T03 DE1T0.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 138 Freescale Se miconduc tor 9.5.1 USB Embedded Device Address Register (DADDR) DEVEN — Enable U SB Embedded Device These bit enable or disable the embedded device function. It is used together with PEN1-PEN 4 to control the e numeration sequence.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 139 TXD0F — Embedded Device Endpo int 0 Data Transmit Flag This read only bit is set after t he data stored in embedded device Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 140 Freescale Se miconduc tor 1 = Receive Embedded Device E ndpoint 0 can generate a CPU interrupt request 0 = Receive Embedded Device E ndpoint 0.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 141 1 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has occurred 0 = Transmit on Endpoint 1 or Endpoint 2 .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 142 Freescale Se miconduc tor 1 = DATA1 Token active for ne xt embedded device Endpoint 0 transmit 0 = DATA0 Token active for ne xt embedded devic.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 143 TP0SIZ3-TP0SIZ0 — Em bedded Device Endpoint 0 Transmit Data Packet Size These read/write bits st ore the number of trans mit data bytes for the next IN token request for embedded device Endpoint 0.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 144 Freescale Se miconduc tor 1 = The data buffers are used fo r embedded device Endpoint 2 0 = The data buffers are used fo r embedded device End.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 145 DRSEQ — Embedded Devi ce Endpoint 0 Receive Sequence Bit This read only bit indica tes the type of data packet last received for embedded device Endpoint 0 (DATA0 or DATA1).
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 146 Freescale Se miconduc tor 9.5.7 USB Embedded Device Control Register 2 (DCR2) ENABLE2 — Embedded Devi ce Endpoint 2 Enable This read/write bit enabl es embedded device Endp oint 2 and allows the USB to respond to IN packets addressed to this endpoint.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 147 DSTALL1 — Embedded De vice Endpoint 1 Force Stall Bit This read/write bit caus es embedded device Endpoint 1 to return a STALL handshake when polle d by either an IN or OUT token by the USB Host Controller.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 148 Freescale Se miconduc tor 9.5.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7) DE1TD7-DE1TD0 — Embedded Device Endpoint 1/ En.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 149 Advance Information — MC68HC(7)08KH12 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 150 Freescale Se miconduc tor 10.3 Features Features of the monitor ROM include the following: • Normal User-Mode Pin Functionality • One Pin .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 151 Figure 10-1. Moni tor Mode Circuit + + + + 10 M Ω X1 V DD V DD + V HI MC145407 MC74HC125 68HC708 RST IRQ1 /V PP OSC1 OSC2 V SS2 V SSA V DD 1 PA0 V DD 10 k Ω 0.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 152 Freescale Se miconduc tor 10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. If PTC3 is low upon moni tor mode entry, CG MOUT is equal to the crystal frequency.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 153 When the host computer has comple ted downloading code into the MCU RAM, This code can be executed by driving PTA0 low while asserting RST low and then high.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 154 Freescale Se miconduc tor 10.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 10-2 and Figure 10-3 .) Figure 10-2. Moni tor Data Format Figure 10-3.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 155 10.4.4 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 10-5.) When the monitor receives a break sign al, it drives the PTA0 pin high for the duration of tw o bits before echoi ng the break signal.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 156 Freescale Se miconduc tor T ab le 10-3. READ (R ead Memory) Command Descrip tion Read byte from mem or y Operand Specifies 2-b yte addr ess in high b yte:lo w b yte order Data Returned Retu r ns contents of specified ad dre ss Opcode $4A Command Sequence ADDR.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 157 T ab le 10-5. IREAD (I ndex ed Read) Command Description Read next 2 b ytes in me mory from last address accessed Oper.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 158 Freescale Se miconduc tor NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 159 10.4.6 Baud Rate The communication baud rate is cont rolled by crystal frequency and the state of the PTC3 pin upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 160 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 161 Advance Information — MC68HC(7)08KH12 Section 11. Timer Interface Module (TIM) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 162 Freescale Se miconduc tor 11.2 Introduction This section describes the timer inte rface module (TIM2, Version B). The TIM is a two-channel time r that provides a timi ng reference with input capture, output compar e, and pulse-width-m odulation functions.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 163 11.4 Functional Description Figure 11-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 164 Freescale Se miconduc tor T ab le 11-1. TIM I/O Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0010 TIM Status/Control Register.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 165 11.4.1 TIM Counter Prescaler The TIM clock source can be one of th e seven prescaler outputs or the TIM clock pin, PTE0/TCLK. The pre scaler generates seven clock rates from the internal bus cl ock.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 166 Freescale Se miconduc tor 11.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 167 channel 0 registers initially controls the output on t he PTE1/TCH0 pin. Writing to the TIM c hannel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TI M overflows.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 168 Freescale Se miconduc tor Figure 11-2. PWM Peri od and Pulse Width The value in the TIM counter modu lo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is va riable in 256 in crements.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 169 write a new, smaller pulse width value may caus e the compare to be missed.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 170 Freescale Se miconduc tor control register (TSC1) is unused. Whil e the MS0B bit is set, the channel 1 pin, PTE2/TCH1, is avail able as a general-purpose I/O pin. NOTE: In buffered PWM signal gener ation, do not write new pulse width values to the currently active channel registers.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 171 Setting MS0B links chann els 0 and 1 and configur es them for buffered PWM operation. The TIM channel 0 r egisters (TCH0H:TCH0L) initially control the buffered PWM output.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 172 Freescale Se miconduc tor If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM befor e executing the WAIT instruction. 11.7 TIM During Break Interrupts A break interrupt st ops the TIM counter.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 173 minimum TCLK pulse width, TCLK LMIN or TCLK HMIN , is: The maximum TCLK frequency is: PTE0/TCLK is available as a general -purpose I/O pin when not used as the TIM clock input.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 174 Freescale Se miconduc tor • Resets the TIM counter • Prescales the TIM counter clock TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter resets to $0000 after reaching the modulo va lue programmed in the TIM counter modulo registers.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 175 NOTE: Do not set the TSTOP bit before enteri ng wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 176 Freescale Se miconduc tor TCNTH do not affect the latched TC NTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 177 NOTE: Reset the TIM counter bef ore writing to the TIM counter modulo registers.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 178 Freescale Se miconduc tor CHxF — Chann el x Flag Bit When channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 179 MSxB — Mode Select Bit B This read/write bit sele cts buffered output co mpare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to gen eral-purpose I/O.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 180 Freescale Se miconduc tor NOTE: Before enabling a TIM ch annel register for input capture operation, make sure that the PTEx/TCH x pin is stable for at least two bus clocks.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 181 Figure 11-7. CHxMAX Latency 11.9.5 TIM Channel Registers (TCH0H/L–TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the outp ut compare value of the output compare function.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 182 Freescale Se miconduc tor Address: $0017 TCH0H B i t 7 654321 B i t 0 Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 B it9 Bit8 Write: Reset: Indet.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 183 Advance Information — MC68HC(7)08KH12 Section 12. I/O Ports 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 184 Freescale Se miconduc tor 12.2 Introduction Forty-two bidirectional inpu t-output (I/O) pins form five parallel ports. All I/O pins are programmab le as inputs or outputs. NOTE: Connect any unused I/O pins to an appr opriate logic level, either V DD or V SS .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 185 $0007 Data Direction Register D (DDRD) Read: DDRD7 DDRD6 D DRD5 DDRD4 DDRD 3 DDRD2 DDRD 1 DDRD0 Write: R e s e t : 000.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 186 Freescale Se miconduc tor 12.3 Port A Port A is an 8-bit gener al-purpose bidirectional I/O port with software configurable pullups. 12.3.1 Port A Data Register (PTA) The port A data regist er contains a data latch fo r each of the eight port A pins.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 187 DDRA[7:0] — Data Dire ction Register A Bits These read/write bits control port A data direction.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 188 Freescale Se miconduc tor 12.4 Port B Port B is an 8-bit gener al-purpose bidirectional I/O port with software configurable pullups. 12.4.1 Port B Data Register (PTB) The port B data register co ntains a data latch for each of the eight port B pins.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 189 12.4.2 Data Direction Register B (DDRB) Data direction register B determine s whether each port B pin is an input or an output. Writing a l ogic one to a DDRB bit enabl es the output buffer for the corresponding port B pin; a logic zero di sables the output buffer.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 190 Freescale Se miconduc tor When bit DDRBx is a lo gic one, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic zero, reading address $0001 reads the voltage level on the pin.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 191 PTC[4:0] — Port C Data Bits These read/write bits are software-p rogrammable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 192 Freescale Se miconduc tor Figure 12-9. Port C I/O Circuit When bit DDRCx is a logic one, r eading address $0002 reads the PTCx data latch. When bit DDRCx is a logic zero, reading address $0002 reads the voltage level on the pin.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 193 12.6.1 Port D Data Register (PTD) The port D data register c ontains a data latch for each of the eight port D pins. PTD[7:0] — Port D Data Bits These read/write bits are software programmable.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 194 Freescale Se miconduc tor DDRD[7:0] — Data Dire ction Register D Bits These read/write bits control port D data direction.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 195 12.7 Port E Port E is a 5-bit special function port t hat shares four of its pins with the keyboard interrupt module (KBI) and sh ares three of its pins with the timer interface module (TIM).
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 196 Freescale Se miconduc tor PTE[4:0] — Port E Data Bits PTE[4:0] are read/write, software- programmable bits. Data direction of each port E pin is under the control of the co rresponding bit in data direction register E.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 197 DDRE[4:0] — Data Dire ction Register E Bits These read/write bits control port E data direction.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 198 Freescale Se miconduc tor 12.7.3 Port-E Optical Interface Enable Register Port E pins PTE3–PTE0, each has an optical c oupling interface circuit which is specially built for optical mouse application.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 199 XREF2–XREF0 — Reference Voltage Selection X These bits sets the slicing refer ence voltage for optical interface associated with PTE0 and PTE1.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 200 Freescale Se miconduc tor Figure 12-17. Optical In terface Voltage References X-VREF VOLTAGE DIVIDER ENABLE VOLTAGE SELECTOR Y-VREF VOLTAGE SE.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 201 Figure 12-18. Port E Op tical Coupling Interface PTE0 PORT LOGIC PTE0 OPTICAL INTERFACE OUTPUT BUFFER MUX SELECT PTE1 .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 202 Freescale Se miconduc tor 12.8 Port F Port F is an 8-bit general-purpose bidi rectional I/O port that shares its pins with th e keyboard in terrupt module (KBI). All Port F pins have built- in schmitt triggered input and software configurable pull-up.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 203 12.8.2 Data Direction Register F (DDRF) Data direction register F determines whether each port F pin is an input or an output. Writing a logic one to a DDRF bit enables the output buffer for the corresponding port F pin; a logic zero dis ables the output buffer.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 204 Freescale Se miconduc tor When bit DDRFx is a logic one, reading address $0009 re ads the PTFx data latch. When bit DDRF x is a logic zero, r eading address $0009 reads the voltage level on the pin.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 205 LDD — LED Direct Drive Control This read/write bit cont rols the output current capability of port C.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 206 Freescale Se miconduc tor.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 207 Advance Information — MC68HC(7)08KH12 Section 13. Computer Operating Properly (COP) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 208 Freescale Se miconduc tor 13.3 Functional Description Figure 13-1 shows the structure of the COP module.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 209 The COP counter is a fr ee-running 6-bit counter preceded by the 12-bit SIM counter.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 210 Freescale Se miconduc tor 13.4.3 Power-On Reset The power-on reset (POR) ci rcuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after power-up. 13.4.4 Internal Reset An internal reset clears the SIM counter and the COP counter.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 211 COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Rese t clears COPRS. 1 = COP reset cycle is (2 13 –2 4 ) × CGMXCLK 0 = COP reset cycle is (2 18 –2 4 ) × CGMXCLK COPD — COP Disable Bit COPD disables the COP module.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 212 Freescale Se miconduc tor 13.8 Low-Power Modes The WAIT and STOP in structions put the MCU in low-power consumption standby modes. 13.8.1 Wait Mode The COP continues to operate duri ng wait mode.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 213 Advance Information — MC68HC(7)08KH12 Section 14. External Interrupt (IRQ) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 214 Freescale Se miconduc tor 14.4 Functional Description A logic zero applied to th e external interrupt pin can latch a CPU interrupt request. Figure 14-1 shows the structure of the IRQ module. Interrupt signals on the IR Q1 /V PP pin are latched into the IRQ1 latch.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 215 Figure 14-1. IRQ Module Block Diagram 14.4.1 IRQ1 /V PP Pin A logic zero on the IRQ1 /V PP pin can latch an inte rrupt request into the IRQ1 latch. A vector fetc h, software clear, or reset clears the IRQ1 latch.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 216 Freescale Se miconduc tor • Vector fetch or software clear — A vector fetc h generates an interrupt acknowledge signal to cl ear the latch.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 217 14.5 IRQ Module During Break Interrupts The system integration module (SIM) c ontrols whether the IRQ1 latch can be cleared during the br eak state. The BCFE bi t in the break flag control register (BFCR) enables software to clear the latches during the break state.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 218 Freescale Se miconduc tor IRQF1 — IRQ1 Flag This read-only status bi t is high when the IRQ1 interrupt is pending. 1 = IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writing a logic one to this write-onl y bit clears the IRQ1 latch.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 219 Advance Information — MC68HC(7)08KH12 Section 15. Keyboard Interrupt Module (KBI) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 220 Freescale Se miconduc tor 15.2 Introduction The keyboard module provides twen ty independently maskable external interrupts which are accessibl e via PTD7-PTD0, PTE3-PTE0 and PTF7-PTF0.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 221 T ab le 15-1. KBI I/O Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $000C Port D Keyboard Status and Co.
Adv ance Inf ormation M C68HC(7)08KH1 2 — Re v . 1.1 222 Freescale Se miconducto r 15.4 Port-D Keyboard Interrupt Block Diagram Figure 15-1. Port-D Keyboar d Interrupt Bl ock Diagram KBDIE0 KBDIE7 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 223 15.4.1 Port-D Keyboard Interrupt Functional Description Writing to the KBDIE7–KBDIE0 bits in the keyboard interrupt enable register independently enables or disables each port D pin as a keyboard interrupt pin.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 224 Freescale Se miconduc tor • Return of all enabled keyboard interr upt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 225 3. Write to the ACKD bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKD bit. An interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 226 Freescale Se miconduc tor KEYDF — Port-D Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port-D.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 227 KBDIE7–KBDIE0 — Port-D Ke yboard Interrupt Enable Bits Each of these read/write bits enables the corres ponding keyboard interrupt pin on port-D to latch inte rrupt requests.
Adv ance Inf ormation M C68HC(7)08KH1 2 — Re v . 1.1 228 Freescale Se miconducto r 15.5 Port-E Keyboard Interrupt Block Diagram Figure 15-4. Port-E Keyboar d Interrupt Block Diagram KBEIE0 KBEIE3 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 229 15.5.1 Port-E Keyboard Interrupt Functional Description Writing to the KBEIE3–KBEIE0 bits in the keyboard interrupt enable register independently enables or disables each port E pin as a keyboard interrupt pin.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 230 Freescale Se miconduc tor • Return of all enabled keyboard interr upt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 231 4. Write to the ACKE bit in the keyboard status and control register to clear any false interrupts. 5. Clear the IMASKE bit. An interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 232 Freescale Se miconduc tor ACKE — Port-E Key board Acknowledge Bit Writing a logic 1 to th is write-only bit clears the keyboard interrupt request on port-E. ACKE al ways reads as logic 0. Reset clears ACKE.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 233 KBEIE3–KBEIE0 — Port-E Ke yboard Interrupt Enable Bits Each of these read/write bits enables the corres ponding keyboard interrupt pin on port-D to latch inte rrupt requests.
Adv ance Inf ormation M C68HC(7)08KH1 2 — Re v . 1.1 234 Freescale Se miconducto r 15.6 Port-F Keyboard Interrupt Block Diagram Figure 15-7. Port-F Keyboard Interrupt Block Diagram KBFIE0 KBFIE7 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 235 15.6.1 Port-F Keyboard Interrupt Functional Description Writing to the KBFIE7–K BFIE0 bits in the ke yboard interrupt enable register independently enables or disables each port F pin as a keyboard interrupt pin.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 236 Freescale Se miconduc tor • Return of all enabled keyboard interr upt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 237 4. Write to the ACKF bit in the keyboard status and control register to clear any false interrupts. 5. Clear the IMASKF bit. An interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 238 Freescale Se miconduc tor ACKF — Port-F Keyboard Acknowledge Bit Writing a logic 1 to th is write-only bit clears the keyboard interrupt request on port-F. A CKF always reads as logi c 0. Reset clears ACKF.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 239 15.6.3.3 Port-F Pull-up Enable Register The pulll-up enable regi ster enables or disabl es the pull-up device for port F. PFPE7–PFPE0 — Port F pull-up enable bits These read/write bits enable/disable the pull-up device.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 240 Freescale Se miconduc tor the break flag control regi ster (BFCR) enables software to clear status bits during the break state. To allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the BCFE bit.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 241 Advance Information — MC68HC(7)08KH12 Section 16. Break Module (BREAK) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 242 Freescale Se miconduc tor 16.3 Features Features of the break m odule include the following: • Accessible I/O Registers during the Break Interrupt • CPU-Generated Break Interrupts • Software-Generated Break Interrupts • COP Disabling during Break Interrupts 16.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 243 Figure 16-1. Break Module Block Diagram IAB[15:8] IAB[7:0] 8-BIT COMPARATOR 8-BIT COMPARATOR CONTROL BREAK ADDRESS REGISTER LOW BREAK ADDRESS REGISTER HIGH IAB[15:0] BKPT (TO SIM) T ab le 16-1.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 244 Freescale Se miconduc tor 16.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be clea red during the break stat e.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 245 16.5.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits. BRKE — Break Enable Bit This read/write bit enabl es breaks on break address register matches.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 246 Freescale Se miconduc tor 16.6 Low-Power Modes The WAIT and STOP in structions put the MCU in low-power- consumption standby modes. 16.6.1 Wait Mode If enabled, the break module is active in wait mode.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 247 Advance Information — MC68HC(7)08KH12 Section 17. Preliminary Electrical Specifications 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 248 Freescale Se miconduc tor 17.3 Absolute Maximum Ratings Maximum rating s are t he extreme limits to which the MCU can be exposed without perman ently damaging it. NOTE: This device is not guar anteed to operate properly at the maximum ratings.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 249 17.4 Functional Operating Range 17.5 Thermal Characteristics Characteristic Symbol Value Unit Operat ing T emperatur e Range T A 0 to 85 ° C Operat ing V oltage Range V DD 4.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 250 Freescale Se miconduc tor 17.6 DC Electrical Characteristics Characteristic Symbol Min Typ (2) Max Unit Output High V oltage (I LOAD = – 2.0 mA) All I/O Pins V OH V DD – 0.8 — — V Output Lo w V oltage (I LOAD = 1.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 251 17.7 Control Timing 17.8 Oscillator Characteristics Characteristic Symbol Min Max Unit Internal Operating F requency (2) f OP —6 M H z RST Input Pulse Width Lo w (3) t IRL 50 — ns NOTES: 1.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 252 Freescale Se miconduc tor 17.9 USB DC Electrical Characteristics Characteristic Symbol Conditi ons Min Typ Max Unit Hi-Z State Data Line Leakage I LO 0V< V IN <3.3V – 10 + 10 µ A Diff erential Input Sensitivity V DI |(D+) – (D –)| 0.
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 253 17.10 USB Low Speed Source Electrical Characteristics Characteristic Symbol Conditions (Notes 1, 2,3 ) Min Typ Max Uni.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 254 Freescale Se miconduc tor 17.11 USB High Speed Source Electrical Characteristics Characteristic Symbol Conditions (Notes 1, 2,3 ) Min Typ Max .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 255 17.12 HUB Repeater Electrical Characteristics Low Speed HUB Electri cal Characteristics (Root por t and downstream por.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 256 Freescale Se miconduc tor 17.13 USB Signaling Levels 17.14 TImer Interface Module Characteristics Bus State Signaling Levels Transmit Receive .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 257 17.15 Clock Generation Module Characteristics 17.15.1 CGM Component Specifications 17.15.2 CGM Electrical Specifications Characteristic Symbol Min Typ Max Unit Cr ystal ref erence frequency (1) 1.
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 258 Freescale Se miconduc tor 17.15.3 Acquisition/Lock Time Specifications Description Symbol Min Typ Max Not es Filter Capacitor Multiply F actor C FA C T — 0.0145 — F/s V Acquisition Mode Time F actor K AC Q —0 .
MC68HC(7 )08KH12 — R e v . 1.1 Advance Information Freescale Semicon ductor 259 Advance Information — MC68HC(7)08KH12 Section 18. Mechanical Specifications 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adv ance Inf ormation MC68HC(7)08KH1 2 — Re v . 1.1 260 Freescale Se miconduc tor 18.3 Plastic Quad Flat Pack (QFP) Figure 18-1. 64-Pin Quad-Flat-Pack (Case 840C-04) G H E C DET AIL A L A 48 S L –D– –A– –B– 0.05 (0.002) A–B S A–B M 0.
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