Benutzeranleitung / Produktwartung CY7C604XX des Produzenten Cypress
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enCoRe™ V Low V oltage Microcontroller CY7C604XX Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-12395 Rev *H Revised Jan.
CY7C604XX Document Number: 001-12395 Rev *H Page 2 of 30 Functional Overview The enCoRe V L V family of devices are designed to replace multiple traditional low voltag e microcontroller system compo- nents with one, low cost single chip programmable compon ent.
CY7C604XX Document Number: 001-12395 Rev *H Page 3 of 30 Development T ools PSoC Designer is a Microsoft ® Windows-ba sed, integrated development environment for th e Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Wi ndows Vista.
CY7C604XX Document Number: 001-12395 Rev *H Page 4 of 30 Designing with PSoC Designer The development process for the en CoRe V de vice d iffers from that of a traditional fixed f unction microprocessor. Powerful PSoC Designer tools get the core of your design up and running in minutes instead of hours.
CY7C604XX Document Number: 001-12395 Rev *H Page 5 of 30 Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Units of Measure A units of measure table is locat ed in the Electrical S pecifications section.
CY7C604XX Document Number: 001-12395 Rev *H Page 6 of 30 Pin Configuration 16-Pin Part Pinout Figure 1. CY7C60413 16-Pin enCoRe V L V Device T able 1. 16-Pin Part Pino ut (QFN) Pin No.
CY7C604XX Document Number: 001-12395 Rev *H Page 7 of 30 32-Pin Part Pinout Figure 2. CY7C60445 32-Pin enCoRe V L V Device T able 2. 32-Pin Part Pino ut (QFN) Pin No.
CY7C604XX Document Number: 001-12395 Rev *H Page 8 of 30 17 Reset Input XRES Active high external reset with internal p ull down 18 I/O P3[0] Digital I/O 19 I/O P3[2] Digital I/O 20 I/O P2[0] Digital .
CY7C604XX Document Number: 001-12395 Rev *H Page 9 of 30 48-Pin Part Pinout Figure 3. CY7C60455/CY7C60456 48-Pin enCoRe V L V Device T able 3. 48-Pin Part Pino ut (QFN) Pin No.
CY7C604XX Document Number: 001-12395 Rev *H Page 10 of 30 18 Power Vss Supply ground 19 NC NC No connection 20 NC NC No connection 21 Power Vdd Supply voltage 22 IOHR P1[0] (3, 4) Digit al I/O, ISSP D.
CY7C604XX Document Number: 001-12395 Rev *H Page 1 1 of 30 Register Reference The section discusses the register s of the enCoRe V L V device. It lists all the registers in mapping tables, in address order . Register Conventions The register conventions specific to th is section are listed in the following table.
CY7C604XX Document Number: 001-12395 Rev *H Page 12 of 30 T able 5. Register Map Bank 0 T able: User Sp ace Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex).
CY7C604XX Document Number: 001-12395 Rev *H Page 13 of 30 T able 6 . Register Ma p Bank 1 T able: Configuration S pace Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name A.
CY7C604XX Document Number: 001-12395 Rev *H Page 14 of 30 Electrical Specifications This section presents the DC and AC electric al specifications of the enCoRe V L V dev ices. For the most up to date electrical specifications, verify that you have the most recent data sheet availa ble by visiting the company web site at http:/ /www .
CY7C604XX Document Number: 001-12395 Rev *H Page 15 of 30 ADC Elect rical Specificat ions T able 8. ADC Electr ical Specifications Symbol Description Min Ty p Max Units Conditions Input Input V oltage Range Vss 1.3 V This gives 72% of maximum code Input Capacit ance 5 pF Resolutio n 8 Bits 8-Bit Sample Rate 23.
CY7C604XX Document Number: 001-12395 Rev *H Page 16 of 30 Maximum Ratings S torage T emperature (T STG ) (5) -55 o C to 125 o C (T ypical +25 o C) Supply V oltage Relative to Vss (Vdd) ............. -0.5V to +4.0V DC Input V olt age (V IO ) ..........
CY7C604XX Document Number: 001-12395 Rev *H Page 17 of 30 DC General Pur pose I/O S pecifications The following tables list guaranteed maximum and minimum specificat io ns for the voltage and temper ature ranges: 1.71V to 3.6V a nd 0 ° C ≤ T A ≤ 70 ° C.
CY7C604XX Document Number: 001-12395 Rev *H Page 18 of 30 T able 1 1. 2.4V to 3.0V DC GPIO Specifications Symbol Description Conditions Min Ty p Max Unit s R PU Pull Up Resistor 4 5.6 8 k Ω V OH1 High Output V oltage Port 2 or 3 Pins IOH < 10 μ A, maximum of 10 mA source current in all I/Os Vdd - 0.
CY7C604XX Document Number: 001-12395 Rev *H Page 19 of 30 T able 1 2. 1.71V to 2.4V D C GPIO S pecifications Symbol Description Conditions Min Ty p Max Units R PU Pull Up Resistor 4 5.6 8 k Ω V OH1 High Output V oltage Port 2 or 3 Pins IOH = 10 μ A, maximum of 10 mA source current in all I/Os Vdd - 0.
CY7C604XX Document Number: 001-12395 Rev *H Page 20 of 30 DC POR and L VD Specifications Ta b l e 1 3 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. DC Programming Sp ecifications Ta b l e 1 4 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
CY7C604XX Document Number: 001-12395 Rev *H Page 21 of 30 AC Electrical C haracteristics AC Chip Level Specifications Ta b l e 1 5 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
CY7C604XX Document Number: 001-12395 Rev *H Page 22 of 30 Figure 6. GPIO Ti ming Diagram AC External Clock Specific at io n s Ta b l e 1 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
CY7C604XX Document Number: 001-12395 Rev *H Page 23 of 30 Figure 7. Timing Diag ram - AC Programming Cycle AC SPI Specif ications Ta b l e 1 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. T able 19.
CY7C604XX Document Number: 001-12395 Rev *H Page 24 of 30 AC I 2 C S pecifications Ta b l e 2 0 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Figure 8. Definition of Timing for Fast/S tandard Mode on the I 2 C Bus T able 20.
CY7C604XX Document Number: 001-12395 Rev *H Page 25 of 30 Package Diagram This section illustrates the packaging spec ifications fo r the enCoRe V L V device, al ong with the thermal impeda nces for each pa ckage. Important Note Emulation tools may require a larger area on the target PCB than the chip’ s footprint.
CY7C604XX Document Number: 001-12395 Rev *H Page 26 of 30 Figure 10. 32-Pin (5 x 5 x 0.55 mm) QFN (001-4216 8) 001-42168 *C [+] Feedback.
CY7C604XX Document Number: 001-12395 Rev *H Page 27 of 30 Figure 1 1. 48-Pin (7 x 7 x 0.9 mm) QFN (001-13191) Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leavin g the factory .
CY7C604XX Document Number: 001-12395 Rev *H Page 28 of 30 Thermal Impedances Solder Reflow Peak T emperature Following is the minimum solder reflow peak temperature to achieve go od solde rability . Ordering Information Package T ypical θ JA (23) 16 QFN 32.
CY7C604XX Document Number: 001-12395 Rev *H Page 29 of 30 Document History Page Document Title: CY7C604XX, enCoRe™ V Low V oltage Microcontroller Document Numb er: 001-12395 Rev .
Document Number: 001-12395 Rev *H Revised January 30, 20 09 Page 30 of 30 enCoRe™, PSoC De sig ne r™ a nd Pr o gram m ab le System - on - Ch ip™ ar e tr ad em arks an d PSoC® is a regi ste red tr ad em ar k of Cy pr ess S emi cond uctor Corpor at io n.
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